/*
 * Copyright (C) 2019 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2019-02-11 15:07:05
 *
 */


#ifndef ANLG_PHY_G3_H
#define ANLG_PHY_G3_H

#define CTL_BASE_ANLG_PHY_G3 0x634B0000


#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL0                  ( CTL_BASE_ANLG_PHY_G3 + 0x0000 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL2                  ( CTL_BASE_ANLG_PHY_G3 + 0x0004 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL4                  ( CTL_BASE_ANLG_PHY_G3 + 0x0008 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL5                  ( CTL_BASE_ANLG_PHY_G3 + 0x000C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL6                  ( CTL_BASE_ANLG_PHY_G3 + 0x0010 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL0                  ( CTL_BASE_ANLG_PHY_G3 + 0x0014 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL1                  ( CTL_BASE_ANLG_PHY_G3 + 0x0018 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL2                  ( CTL_BASE_ANLG_PHY_G3 + 0x001C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL3                  ( CTL_BASE_ANLG_PHY_G3 + 0x0020 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL4                  ( CTL_BASE_ANLG_PHY_G3 + 0x0024 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL5                  ( CTL_BASE_ANLG_PHY_G3 + 0x0028 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL6                  ( CTL_BASE_ANLG_PHY_G3 + 0x002C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL0              ( CTL_BASE_ANLG_PHY_G3 + 0x0030 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL2              ( CTL_BASE_ANLG_PHY_G3 + 0x0034 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL4              ( CTL_BASE_ANLG_PHY_G3 + 0x0038 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL5              ( CTL_BASE_ANLG_PHY_G3 + 0x003C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL6              ( CTL_BASE_ANLG_PHY_G3 + 0x0040 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL0              ( CTL_BASE_ANLG_PHY_G3 + 0x0044 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL2              ( CTL_BASE_ANLG_PHY_G3 + 0x0048 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL4              ( CTL_BASE_ANLG_PHY_G3 + 0x004C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL5              ( CTL_BASE_ANLG_PHY_G3 + 0x0050 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL6              ( CTL_BASE_ANLG_PHY_G3 + 0x0054 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL0                  ( CTL_BASE_ANLG_PHY_G3 + 0x0058 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL1                  ( CTL_BASE_ANLG_PHY_G3 + 0x005C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL2                  ( CTL_BASE_ANLG_PHY_G3 + 0x0060 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL3                  ( CTL_BASE_ANLG_PHY_G3 + 0x0064 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL4                  ( CTL_BASE_ANLG_PHY_G3 + 0x0068 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL5                  ( CTL_BASE_ANLG_PHY_G3 + 0x006C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL6                  ( CTL_BASE_ANLG_PHY_G3 + 0x0070 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_TEST_CLK_CTRL                ( CTL_BASE_ANLG_PHY_G3 + 0x0074 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_ANA_TESTMUX                  ( CTL_BASE_ANLG_PHY_G3 + 0x0078 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_ANA_PLL_RSVD                 ( CTL_BASE_ANLG_PHY_G3 + 0x007C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL0                  ( CTL_BASE_ANLG_PHY_G3 + 0x0080 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL2                  ( CTL_BASE_ANLG_PHY_G3 + 0x0084 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL3                  ( CTL_BASE_ANLG_PHY_G3 + 0x0088 )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL5                  ( CTL_BASE_ANLG_PHY_G3 + 0x008C )
#define REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL6                  ( CTL_BASE_ANLG_PHY_G3 + 0x0090 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_THM_CTRL0               ( CTL_BASE_ANLG_PHY_G3 + 0x0094 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL0             ( CTL_BASE_ANLG_PHY_G3 + 0x009C )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL2             ( CTL_BASE_ANLG_PHY_G3 + 0x00A0 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL4             ( CTL_BASE_ANLG_PHY_G3 + 0x00A4 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL5             ( CTL_BASE_ANLG_PHY_G3 + 0x00A8 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL6             ( CTL_BASE_ANLG_PHY_G3 + 0x00AC )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL0             ( CTL_BASE_ANLG_PHY_G3 + 0x00B0 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL2             ( CTL_BASE_ANLG_PHY_G3 + 0x00B4 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL4             ( CTL_BASE_ANLG_PHY_G3 + 0x00B8 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL5             ( CTL_BASE_ANLG_PHY_G3 + 0x00BC )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL6             ( CTL_BASE_ANLG_PHY_G3 + 0x00C0 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_TEST_CLK_CTRL           ( CTL_BASE_ANLG_PHY_G3 + 0x00C4 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX0       ( CTL_BASE_ANLG_PHY_G3 + 0x00C8 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX1       ( CTL_BASE_ANLG_PHY_G3 + 0x00CC )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX2       ( CTL_BASE_ANLG_PHY_G3 + 0x00D0 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX3       ( CTL_BASE_ANLG_PHY_G3 + 0x00D4 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX4       ( CTL_BASE_ANLG_PHY_G3 + 0x00D8 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX5       ( CTL_BASE_ANLG_PHY_G3 + 0x00DC )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX6       ( CTL_BASE_ANLG_PHY_G3 + 0x00E0 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX7       ( CTL_BASE_ANLG_PHY_G3 + 0x00E4 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL_DBG_SEL      ( CTL_BASE_ANLG_PHY_G3 + 0x00E8 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX0       ( CTL_BASE_ANLG_PHY_G3 + 0x00EC )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX1       ( CTL_BASE_ANLG_PHY_G3 + 0x00F0 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX2       ( CTL_BASE_ANLG_PHY_G3 + 0x00F4 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX3       ( CTL_BASE_ANLG_PHY_G3 + 0x00F8 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX4       ( CTL_BASE_ANLG_PHY_G3 + 0x00FC )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX5       ( CTL_BASE_ANLG_PHY_G3 + 0x0100 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX6       ( CTL_BASE_ANLG_PHY_G3 + 0x0104 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX7       ( CTL_BASE_ANLG_PHY_G3 + 0x0108 )
#define REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL_DBG_SEL      ( CTL_BASE_ANLG_PHY_G3 + 0x010C )

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_N(x)                               (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL0_RESERVED1(x)                 (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_ICP(x)                             (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL0_RESERVED0(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL2_RESERVED1(x)                 (((x) & 0x7) << 15)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_POSTDIV                            BIT(14)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL2_RESERVED0(x)                 (((x) & 0x3FFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_LPF(x)                             (((x) & 0x7) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_LDO_TRIM(x)                        (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL4_RESERVED1(x)                 (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_FBDIV_EN                           BIT(4)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CP_EN                              BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CP_OFFSET(x)                       (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_BIST_CTRL(x)                       (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_BIST_EN                            BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_BIST_CNT(x)                        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_OD_R8PLL_CLKOUT_EN                       BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R8PLL_RESERVED(x)                        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_N(x)                               (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_ICP_FS(x)                          (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_ICP(x)                             (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_SDM_EN                             BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_MOD_EN                             BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_DIV_S                              BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL1 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_NINT(x)                            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_KINT(x)                            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_IL_DIV                             BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL2_RESERVED2(x)                 (((x) & 0x3) << 14)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL2_RESERVED1(x)                 (((x) & 0x7) << 11)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL2_RESERVED0(x)                 (((x) & 0x7FF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL3 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_DIV_SEL(x)                         (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_SSC_CTRL(x)                        (((x) & 0xFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_R2_SEL(x)                          (((x) & 0x3) << 14)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_R3_SEL(x)                          (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_LDO_TRIM(x)                        (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL4_RESERVED0(x)                 (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_FBDIV_EN                           BIT(4)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CP_OFFSET(x)                       (((x) & 0x7) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CP_EN                              BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_BIST_CTRL(x)                       (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_BIST_EN                            BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_BIST_CNT(x)                        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_OD_V3PLL_CLKOUT_EN                       BIT(11)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_V3PLL_RESERVED(x)                        (((x) & 0x7FF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_N(x)                           (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL0_RESERVED1(x)             (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_ICP(x)                         (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL0_RESERVED0(x)             (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL2_RESERVED2(x)             (((x) & 0x7) << 18)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL2_RESERVED1(x)             (((x) & 0x7) << 15)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_POSTDIV                        BIT(14)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL2_RESERVED0(x)             (((x) & 0x3FFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_LPF(x)                         (((x) & 0x7) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_LDO_TRIM(x)                    (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL4_RESERVED0(x)             (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_FBDIV_EN                       BIT(4)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CP_OFFSET(x)                   (((x) & 0x7) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CP_EN                          BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_BIST_CTRL(x)                   (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_BIST_EN                        BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_BIST_CNT(x)                    (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_OD_NR_CPUPLL_CLKOUT_EN                   BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_CPUPLL_RESERVED(x)                    (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_N(x)                           (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL0_RESERVED1(x)             (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_ICP(x)                         (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL0_RESERVED0(x)             (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL2_RESERVED2(x)             (((x) & 0x7) << 18)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL2_RESERVED1(x)             (((x) & 0x7) << 15)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_POSTDIV                        BIT(14)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL2_RESERVED0(x)             (((x) & 0x3FFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_LPF(x)                         (((x) & 0x7) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_LDO_TRIM(x)                    (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL4_RESERVED1(x)             (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_FBDIV_EN                       BIT(4)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CP_OFFSET(x)                   (((x) & 0x7) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CP_EN                          BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_BIST_CTRL(x)                   (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_BIST_EN                        BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_BIST_CNT(x)                    (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_OD_NR_DSPPLL_CLKOUT_EN                   BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NR_DSPPLL_RESERVED(x)                    (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_N(x)                               (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_ICP_FS(x)                          (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_ICP(x)                             (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_SDM_EN                             BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_MOD_EN                             BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_DIV_S                              BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL1 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_NINT(x)                            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_KINT(x)                            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_IL_DIV                             BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL2_RESERVED2(x)                 (((x) & 0x3) << 14)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL2_RESERVED1(x)                 (((x) & 0x7) << 11)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL2_RESERVED0(x)                 (((x) & 0x7FF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL3 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_DIV_SEL(x)                         (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_SSC_CTRL(x)                        (((x) & 0xFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_R2_SEL(x)                          (((x) & 0x3) << 14)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_R3_SEL(x)                          (((x) & 0x3) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_LDO_TRIM(x)                        (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL4_RESERVED0(x)                 (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_FBDIV_EN                           BIT(4)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CP_OFFSET(x)                       (((x) & 0x7) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CP_EN                              BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_BIST_CTRL(x)                       (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_BIST_EN                            BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_BIST_CNT(x)                        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_OD_NRPLL_CLKOUT_EN                       BIT(11)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_NRPLL_RESERVED(x)                        (((x) & 0x7FF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_TEST_CLK_CTRL */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_TEST_CLK_EN                              BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_TEST_CLK_DIV(x)                          (((x) & 0x3))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_ANA_TESTMUX */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_ANALOG_TESTMUX(x)                        (((x) & 0x7FF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_ANA_PLL_RSVD */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_ANALOG_PLL_RESERVED(x)                   (((x) & 0xFFFFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_N(x)                               (((x) & 0x7FF) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_ICP(x)                             (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CP_OFFSET(x)                       (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_POSTDIV                            BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_FBDIV_EN                           BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CP_EN                              BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_OD_R5PLL_CLKOUT_EN                       BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL3 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_LPF(x)                             (((x) & 0x7) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_LDO_TRIM(x)                        (((x) & 0xF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_BIST_CTRL(x)                       (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_BIST_EN                            BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_BIST_CNT(x)                        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_PLL_TOP_R5PLL_RESERVED(x)                        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_THM_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_THM_BG_RBIAS_MODE                   BIT(13)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_THM_TEST_SEL(x)                     (((x) & 0x3) << 11)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_THM_BP_MODE                         BIT(10)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_THM_BP_DATA(x)                      (((x) & 0x3FF))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N(x)                          (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL0_RESERVED1(x)            (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP(x)                        (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL0_RESERVED(x)             (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL2_RESERVED2(x)            (((x) & 0x7) << 19)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_REFCK_SEL                     BIT(18)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL2_RESERVED1(x)            (((x) & 0x7) << 15)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV                       BIT(14)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL2_RESERVED0(x)            (((x) & 0x1FFF) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_TEST_CLKOUT_EN                BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_LPF(x)                        (((x) & 0x7) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_LDO_TRIM(x)                   (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL4_RESERVED0(x)            (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_FBDIV_EN                      BIT(4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CP_OFFSET(x)                  (((x) & 0x7) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CP_EN                         BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_BIST_CTRL(x)                  (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_BIST_EN                       BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_BIST_CNT(x)                   (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_RESERVED(x)                   (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL0 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N(x)                          (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL0_RESERVED1(x)            (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP(x)                        (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL0_RESERVED(x)             (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL2 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL2_RESERVED2(x)            (((x) & 0x7) << 19)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_REFCK_SEL                     BIT(18)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL2_RESERVED1(x)            (((x) & 0x7) << 15)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV                       BIT(14)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL2_RESERVED0(x)            (((x) & 0x1FFF) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_TEST_CLKOUT_EN                BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL4 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_LPF(x)                        (((x) & 0x7) << 12)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_LDO_TRIM(x)                   (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL4_RESERVED0(x)            (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_FBDIV_EN                      BIT(4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CP_OFFSET(x)                  (((x) & 0x7) << 1)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CP_EN                         BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL5 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_BIST_CTRL(x)                  (((x) & 0xFF) << 17)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_BIST_EN                       BIT(16)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_BIST_CNT(x)                   (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL6 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_RESERVED(x)                   (((x) & 0xFFFF))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_TEST_CLK_CTRL */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_ANALOG_MPLL_RESERVED(x)             (((x) & 0x1FFFFF) << 6)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_TEST_CLK_DIV(x)                     (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_TEST_CLK_SEL                        BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_TEST_CLK_EN                         BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_TEST_THM_EN                         BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX0 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX0(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX0                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX0(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX1 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX1(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX1                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX1(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX2 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX2(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX2                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX2(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX3 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX3(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX3                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX3(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX4 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX4(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX4                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX4(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX5 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX5(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX5                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX5(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX6 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX6(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX6                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX6(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_DVFS_INDEX7 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_N_INDEX7(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_POSTDIV_INDEX7                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_ICP_INDEX7(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL0_CTRL_DBG_SEL */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_DBG_SEL_ANALOG_MPLL0_MPLL0_ICP      BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_DBG_SEL_ANALOG_MPLL0_MPLL0_N        BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_DBG_SEL_ANALOG_MPLL0_MPLL0_POSTDIV  BIT(0)

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX0 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX0(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX0                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX0(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX1 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX1(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX1                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX1(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX2 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX2(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX2                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX2(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX3 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX3(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX3                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX3(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX4 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX4(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX4                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX4(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX5 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX5(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX5                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX5(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX6 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX6(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX6                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX6(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_DVFS_INDEX7 */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_N_INDEX7(x)                   (((x) & 0x7FF) << 4)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_POSTDIV_INDEX7                BIT(3)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_ICP_INDEX7(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_MPLL1_CTRL_DBG_SEL */

#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_DBG_SEL_ANALOG_MPLL1_MPLL1_ICP      BIT(2)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_DBG_SEL_ANALOG_MPLL1_MPLL1_N        BIT(1)
#define BIT_ANLG_PHY_G3_ANALOG_MPLL_THM_TOP_DBG_SEL_ANALOG_MPLL1_MPLL1_POSTDIV  BIT(0)


#endif /* ANLG_PHY_G3_H */


